Gate array

Results: 1402



#Item
151RFIC 2015 INDUSTRY SHOWCASE PRESS KIT Bell Labs: A 16-Element W-Band Phased Array Transceiver Chipset Bell Labs, the industrial research arm of Alcatel-Lucent, will present the world’s first package-less, fully integra

RFIC 2015 INDUSTRY SHOWCASE PRESS KIT Bell Labs: A 16-Element W-Band Phased Array Transceiver Chipset Bell Labs, the industrial research arm of Alcatel-Lucent, will present the world’s first package-less, fully integra

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Source URL: rfic-ieee.org

Language: English - Date: 2015-05-07 14:57:30
152EN164: Design of Computing Systems Lecture 04: Lab Foundations / Programmable logic Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering

EN164: Design of Computing Systems Lecture 04: Lab Foundations / Programmable logic Professor Sherief Reda http://scale.engin.brown.edu Electrical Sciences and Computer Engineering School of Engineering

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Source URL: scale.engin.brown.edu

Language: English - Date: 2014-03-23 13:26:52
153© heieck.net  1 ESR – Efficient acceleration of simulations for risk measurement and management

© heieck.net 1 ESR – Efficient acceleration of simulations for risk measurement and management

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Source URL: www.esr-projekt.de

Language: English - Date: 2014-07-09 02:41:54
154Recent Advances in Accelerating Financial Computation Wayne Luk1 1  Ce Guo1

Recent Advances in Accelerating Financial Computation Wayne Luk1 1 Ce Guo1

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Source URL: lis.ei.tum.de

Language: English - Date: 2014-09-04 05:08:50
155Yosys - A Free Verilog Synthesis Suite Clifford Wolf, Johann Glaser† Johannes Kepler University, Austria Institute for Integrated Circuits ,  †

Yosys - A Free Verilog Synthesis Suite Clifford Wolf, Johann Glaser† Johannes Kepler University, Austria Institute for Integrated Circuits , †

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Source URL: www.clifford.at

Language: English - Date: 2013-10-11 16:34:33
156Yosys Open SYnthesis Suite  Clifford Wolf (http://www.clifford.at/yosys/) Clifford Wolf http://www.clifford.at/yosys/

Yosys Open SYnthesis Suite Clifford Wolf (http://www.clifford.at/yosys/) Clifford Wolf http://www.clifford.at/yosys/

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Source URL: www.clifford.at

Language: English - Date: 2015-02-09 07:25:30
157Xilinx Training Course Listing  Effective April 1, 2015 II

Xilinx Training Course Listing Effective April 1, 2015 II

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Source URL: japan.xilinx.com

Language: English - Date: 2015-04-14 15:20:39
158Technical Papers Electrical Design and Modeling Challenges for 3D System Integration Madhavan Swaminathan Power Grid Parasitic Impact on System Level Power Delivery Thao Pham, Vishram Pandit, Almario F. Delos Angeles Ver

Technical Papers Electrical Design and Modeling Challenges for 3D System Integration Madhavan Swaminathan Power Grid Parasitic Impact on System Level Power Delivery Thao Pham, Vishram Pandit, Almario F. Delos Angeles Ver

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Source URL: www.designcon.com

Language: English - Date: 2014-12-22 13:34:10
159Conference February 4 - February 7, 2008 Exhibition February 6 - February 6, 2008 Santa Clara, California CD-ROM Technical Paper Proceedings Sponsor  www.bertscope.com

Conference February 4 - February 7, 2008 Exhibition February 6 - February 6, 2008 Santa Clara, California CD-ROM Technical Paper Proceedings Sponsor www.bertscope.com

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Source URL: www.designcon.com

Language: English - Date: 2014-12-22 13:34:10
160OpenCores HDL modeling guidelines This document describes the OpenCores HDL modelling guidelines with some examples Brought to You By OpenCores

OpenCores HDL modeling guidelines This document describes the OpenCores HDL modelling guidelines with some examples Brought to You By OpenCores

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Source URL: cdn.opencores.org

Language: English - Date: 2011-06-07 09:12:49